------------------------------------------------//库声明
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

------------------------------------------------//实体定义
entity adder_N is
port
(   clk_in : in std_logic;     	  
	 shuzhi : out integer range 0 to 127
      );        
end adder_N;

------------------------------------------------//结构体定义
architecture  behave of adder_N is

------------------------------------------------//信号量定义
signal count_N:integer := 127;
signal count_1:integer range 0 to 130;

begin

------------------------------------------------//进程1，计数
    process(clk_in)
    begin
        if(clk_in'event and clk_in = '1' ) then		
            if count_1=count_N-1 then 
				    count_1<=0;        
            else count_1<=count_1+1;
            end if;
        end if;
    end process;
	 
------------------------------------------------//赋值	
	 shuzhi<= count_1;

end behave;